VHDL code for 3-to-8 decoder
3-to-8 decoder is a combinational circuit which reverse operation of an 8-to-3 encoder,it converts binary information from n input lines to a maximum of 2n unique output lines. The following VHDL example illustrates how to design a 3-to-8 decoder using select syntax.
3-to-8 decoder
trans38.rar: 3-to-8 decoder vhdl code.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity trans38 is
port(
A:in std_logic_vector(2 downto 0);
EN:in std_logic;
Y:out std_logic_vector(7 downto 0)
);
end trans38;
architecture dec_behave of trans38 is
signal sel:std_logic_vector(3 downto 0);
begin
sel<=A&EN;
with sel select
Y<= "00000001" when "0001",
"00000010" when "0011",
"00000100" when "0101",
"00001000" when "0111",
"00010000" when "1001",
"00100000" when "1011",
"01000000" when "1101",
"10000000" when "1111",
"XXXXXXXX" when others;
end dec_behave;
| Attachment | Size |
|---|---|
 trans38.rar | 362 bytes |
